The present invention relates to a semiconductor integrated circuit having one or more on-chip capacitors thereon, a method of arranging elements formed therein, and a method of manufacturing the same.
In conventional large scale integrated circuits (LSI), there has been a problem that so-called xe2x80x9cground-bouncexe2x80x9d occurs in power supply source trunk lines, due to the switching operation of transistors formed in the LSI, resulting in occurrence of delay and noises. Accordingly, in order to control the ground-bounce, countermeasures such as provisions of capacitors on the package of an LSI and capacitors within an LSI, which are called on-chip capacitors composed of PN junction capacitance or gate capacitance, have been adopted.
The on-chip capacitor itself is made of an aluminum wiring, so that an on-chip capacitor has been heretofore disposed at a peripheral portion of a chip where it does not hinder the disposition of the other wirings. Referring FIG. 8, in conventional LSI, in order to avoid the occurrence of a situation where an on-chip capacitor hinders the disposition of the wirings or limits the arrangement of function blocks, the on-chip capacitor has not been disposed near the transistors causing the ground-bounce. Instead of near the transistors, the in-chip capacitor has been disposed in a spot such as a unused area 43 in an internal region 41 in the LSI where no function block is arranged, a boundary area 44 between the internal region 41 and an Input-Output (I/O) region 42, and a unused area 45 in the I/O region 42 where no I/O buffer is arranged.
In such prior art, since the on-chip capacitor for controlling the ground-bounce is disposed apart from the transistors which actually causes the ground-bounce, there has been a problem that the on-chip capacitor exhibits a less effect for controlling the ground-bounce.
Furthermore, a large capacitance for controlling the ground-bounce, that is, a large on-chip capacitor, is needed, resulting in a problem that the chip mounting the large in-chip capacitor becomes larger.
Still furthermore, when it is intended to dispose an on-chip capacitor in the internal region, wiring is hindered or the wiring length between the function blocks increases because of limitation to the function block arrangement, so that there has been a problem that the performance of the chip is deteriorated.
In the prior art, it is required for an LSI designer to find out an unused region without the aid of any machine and to arrange an on-chip capacitor without the aid of any machine, so that there has been a problems that designing is not easy.
Moreover, since, in the vicinity of the intersection of a power supply source wiring and a ground wiring within a chip, the wiring connection of function blocks and the like is difficult due to the presence of these wirings, the vicinity of such intersection has not been used.
An object of the present invention is to provide a semiconductor integrated circuit in which an on-chip capacitor is built in and a method of manufacturing the same, without reducing its performance and integration density.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit of a standard cell type which comprise: a first wiring group composed of a plurality of first wirings running in a first direction; a second wiring group positioned under said first wiring group, the second wiring group being composed of a plurality of second wirings which run in a second direction different from said first direction; and one or more on-chip capacitors provided in a region which is under a predetermined one of said first wirings and is between two adjacent wirings of said second wirings.
According to a second aspect of the present invention, there is provided method of manufacturing the above-mentioned semiconductor integrated circuit comprises: a first arrangement step of designating said region as an arrangement inhibition region, and arranging one or more function blocks in the other region; a step of canceling the designation of said region having been designated as said arrangement inhibition region in said first arrangement step, after completion of said first arrangement step; and a second arrangement step of arranging one or more on-chip capacitors in both said region of which the designation as said arrangement inhibition region has been canceled and a region which was not used in said first arrangement step.